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AS5030
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.7.2
Power Cycling Mode
The power cycling method shown in Figure 26 cycles the AS5030 by switching it on and off, using an external PNP transistor high side switch.
This mode provides the least power consumption of all three modes; when the sampling interval is more than 400ms, as the current consumption
in off-mode is zero.
It also has the longest start-up time of all modes, as the chip must always perform a “cold start“ from zero, which takes about 1.9 ms.
The optional filter R1/C1 may again be added to reduce peak currents in the 5V power supply line.
Figure 26. Application Example III: Ultra-low Power Encoder
R1
+5V
VDD
VDD
I on
0
t on
t off
10k
C1
ton
toff
VDD
>1μF
on/off
100n
S
N
CS
CLK
Micro
Controller
DIO
AS5030
VSS C1 C2
VSS
VSS
Figure 26 shows an overview of the average supply currents in the three reduced power modes, depending on the sampling interval. The graphs
shows that the Low Power Mode is the best option for sampling intervals <4ms, while the Ultra-low Power Mode is the best option for sampling
intervals between 4~400ms. At sampling intervals > 400ms, the power cycling mode is the best method to minimize the average current
consumption. The curves are based on the figures given in Low Power Mode and Ultra-low Power Mode on page 31 .
Figure 27. Average Current Consumption of Reduced Power Modes
AS 5 0 3 0 av e ra g e c u rre nt c o n su m p tio n
5 ,0
4 ,5
4 ,0
3 ,5
3 ,0
2 ,5
2 ,0
L o w P o we r M o d e
1 ,5
1 ,0
0 ,5
0 ,0
Ultra L o w P owe r M od e
P o wer C yc lin g M o de
1
10
100
1 0 00
samp lin g in terval [m s]
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